InterMCore: Interferences in Design Methodology for High-performance Multi-Core Platforms

When a system is safety-critical, a certification activity must evaluate whether it is compliant with the appropriate standards in that domain. In the avionic and automotive domains, targeted by InterMCore, a key and open challenge is the safe and efficient use of heterogeneous high- performance multi-core platforms (e.g., ARM-based MPSoCs with accelerators), in particular when targeting next generation applications, mixing different criticality requirements and execution models. More precisely, the source of interferences between these applications must be identified and the interferences quantified and possibly reduced to master the temporal behavior of the system. While existing work often focuses on one aspect like identifying timing anomalies during the worst-case execution time computation or analyzing interferences caused by a single hardware component, there is a clear lack of a combined (software and hardware) methodology-aware flow which reasons about the effect of interference on complex MPSoCs to evaluate the predictability of the platform and provide means for interference mitigation.

The InterMCore project aims at building such an interference-centric methodology by:

1. applying both formal methods and benchmarking to capture the timing behavior of these applications over an MPSoCs and
2. defining appropriate rules and transformations to guide the application software synthesis, from the programming model down to the execution platform, for an enhanced (i.e., more predictable) timing behavior with reduced interferences.

A comprehensive framework for assessing but also mitigating the interferences generated by software executed over heterogeneous multi-core platforms will be developed, a key feature for efficiently design the next generation of safety-critical systems.

The INTERMCORE project combines expertise from French and German partners for:

1. identifying all sources of interference in heterogeneous high-performance MPSoCs (ONERA),
2. quantifying the effect of interference in terms of worst-case shared resources (communication and memory) delay using application loads and shared resources models (TU Dortmund),
3. identification of timing anomalies at the software level and considering formal models of the hardware (CEA) and
4. programming models and compilation techniques for a more predictable software and hardware mapping (TU Dresden).

The consortium will target different classes of applications (e.g., control and DNN-based computer vision) from both the avionic (French side) and the automotive (German side) domains and will focus on the XXX platform as a currently challenging and representative example for heterogeneous high-performance MPSoCs.

Coordinators: Mathieu Jan, Selma Saidi

• CEA List (Project Coordinator, French side) : M. JAN (coord.), M. ASAVOAE. Expertise on defining formal models of both hardware platforms and of Instruction Set Architecture (ISA) to combine them for identifying timing anomalies.
• ONERA: C. PAGETTI (coord.), F. BONIOL, B. LESAGE. Expertise on defining predictable and efficient execution models tailored for avionics needs.
• TU Dortmund (Project Coordinator, German side) : S. SAIDI (coord.). Expertise in developing novel techniques for system level performance analysis of highly parallel and heterogeneous embedded architecture.
• TU Dresden : J. CASTRILLON (coord.), C. MENARD. Expertise in methodologies, languages, tools and algorithms for programming complex computing systems

To appear